Circuit for selecting/deselecting a bitline of a non-volatile memory

ABSTRACT

A bit-line selection circuit for a memory device includes a decoding line and a dummy line. The decoding line is between a regulated voltage node, and a programming voltage node generating a programming voltage for a cell in the memory device. The decoding line includes at least one input transistor connected to the regulated voltage node, and is controlled by an enable/disable signal. The dummy line is identical to the decoding line, and is controlled by the enable/disable signal. An equalization circuit is connected between the decoding and dummy lines for setting a current in the dummy line equal to a current in the decoding line. A regulating circuit regulates the programming voltage generated at the programming voltage node in the decoding line. The regulating circuit has a first input for receiving a reference voltage, a second input for receiving a sensed voltage on the programming voltage node in the dummy line, and an output for providing the enable/disable signal. The regulating circuit compensates for differences between the programming voltage and the reference voltage.

FIELD OF THE INVENTION

The invention relates in general to semiconductor memory devices, andmore particularly, to circuits for selecting bit-lines.

BACKGROUND OF THE INVENTION

In semiconductor memory devices circuits are used forselecting/deselecting addressed memory cells. A example circuit is shownin FIG. 1. The circuit comprises a decoding line that includes aplurality of decoding transistors connected in series and which arecontrolled by respective selection signals DEC<3>, DEC<2>, DEC<1>. Thedecoding line also includes at least one transistor controlled by anenable/disable signal PGM, and is connected between a node having aregulated voltage V_(PD) and the series of decoding transistors. When abit-line is selected, the signals PGM, DEC<3>, DEC<2>, DEC<1> enable therespective transistors. In the memory cells, which are substantiallytransistors, there are non-null voltages.

An important field of application of the invention is to non-volatileFlash memory devices. For this reason reference will be made to thesedevices, though other types of semiconductor memory devices areapplicable. The programming voltage on the drain of Flash memory cellsshould be regulated to a precise value. This is very difficult withoutoccupying a large area of silicon.

The voltage on the terminals of any memory cell to be programmed(drain-source voltage) depends on the current flowing in the cell(I_(P<i>)), the number of bits to be programmed at the time, the supplyvoltage of the memory (V_(CC)), and the operating temperature (T) Byobserving the typical example of column decoding used in Flash memorydevices depicted in FIG. 1, the following is noted: PGM<15:0> are on/offsignals that enable the pass-transistor depending on whether a certainbit is to be programmed or not; V_(PD) is the regulated voltage commonlygenerated by a charge pump circuit; DEC<3:1> are selection signals ofthe column decoding; and BL_(<i>) are local bit-lines.

In a partitioned memory device, wherein 16 cells at a time are to beprogrammed, there are 16 pass transistors controlled by the PGM signals.There are also N*16 transistors driven by the selection signal DEC<3>,16*N*M transistors controlled by the selection signal DEC<2>, and16*N*M*L transistors controlled by the selection signal DEC<1>, whereinN, M and L are all multiples of 2.

The problems that arise when a decoding circuit such as that of FIG. 1is used are as follows. It is very difficult to form a regulator for thevoltage BL on each cell to be programmed because 16*N*M*L voltageregulators would be required. This results in an unacceptable areaoccupied silicon.

The current flowing in each cell, designed for a certain nominal value,has a spread that becomes larger as the fabrication process becomes lessprecise. The current flowing in a cell determines a voltage drop on theselection transistors of the relative bit-line path, and in particular,on the selection transistor controlled by the signal DEC<1>. Theselection transistors controlled by DEC<1> are as numerous as the cellsof a row. They should be accommodated in the cell pitch, thus they arevery small. The voltage drop along the bit-line path ΔV(I_(P)) isapproximately given by the drop on the transistors controlled by DEC<1>(low level decoding transistors), as depicted in FIG. 2. The voltage onthe nodes of the cell is about V_(PD)−ΔV(I_(P)), thus the programmingvoltage depends on the current absorbed by the single cell.

The functioning temperature is relevant because when it varies, theresistivity of the low level decoding transistors also varies. Theregulated voltage V_(PD) generally depends on the total currentabsorption by all addressed cells. The voltage drop BL_(<i>) on a cell,which depends on the voltage V_(PD), indirectly depends upon the numberof bits (addressed cells) to be programmed.

If the supply voltage V_(CC) varies, the performance of the charge pumpcircuit also varies as well as the regulated voltage V_(PD). As aconsequence, the programming voltage BL_(<i>) on each cell varies.

Generally, the following equation holds:BL _(<i>) =V _(PD) [ΣI _(P<i>) ,V _(CC) ]−ΔV _(IP) [T,I _(P<i>)]Keeping the voltage drop BL_(<i>) on the i-th cell within an acceptablerange is difficult when the above parameters vary.

These conditions impose a compromise in which the programming voltagemay differ from its nominal value. This compromise may be tolerable insome classes of memory devices. However, it becomes impracticable inmulti-level memory devices where the drain voltage on the cells needs tobe precisely determined.

SUMMARY OF THE INVENTION

In view of the foregoing background, an object of the present inventionis to overcome the drawbacks of bit-line selection/deselection circuits.

This and other objects, features and advantages in accordance with theinvention are provided by a dummy line that is a replica of a bit-linedecoding line, and forcing through it the same current that circulatesin the decoding line. The decoding line and the dummy line aresubstantially identical. Thus, there will be a node of the dummy line atthe same programming potential of an addressed cell of the decodingline. By setting the potential of this node of the dummy line to aconstant reference value, the programming potential of the decoding lineis also effectively fixed.

More precisely, the bit-line selection/deselection circuit for anon-volatile memory may comprise decoding lines connected between a nodeat a regulated voltage and a node on which a programming voltage for anaddressed memory cell is produced. Each circuit includes at least onetransistor controlled by an enable/disable signal, and is connectedbetween a node having a regulated voltage and the series of decodingtransistors.

The dummy line may be identical to the decoding line and may also beidentically controlled. The dummy line is coupled to the same nodehaving the regulated voltage as the decoding line. An equalizationcircuit forces through the dummy line the same current that is forced inthe decoding line. A regulation circuit for the programming voltagecomprises a reference voltage with the voltage present on the node ofthe dummy line corresponding to the node of the decoding line on whichthe programming voltage is produced. The regulation circuit generatesthe enable/disable signal to compensate for differences between theprogramming voltage and the reference voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is described while referring to the attached drawings,wherein:

FIG. 1 is a schematic diagram of a bit-line selection/deselectioncircuit for a non-volatile memory according to the prior art;

FIG. 2 is a schematic diagram illustrating the voltage drop taking placeon a low level decoding transistor according to the prior art;

FIG. 3 is a schematic diagram of the selection/deselection circuitaccording to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An embodiment of the selection/deselection circuit in accordance withthe invention is depicted in FIG. 3. Differently from knownselection/deselection circuits, the illustrated circuit comprises adummy line, the transistors of which are identical to those of thedecoding line and are controlled by the same signals.

The current flowing in the decoding line is replicated in the dummy lineby two current mirrors, the mirror ratios of which are a reciprocal ofone another. To ensure that the dummy line will be biased with the samevoltage that biases the decoding line, a diode-connected load transistorcouples the dummy line with the line at a regulated voltage V_(PD). Thisload transistor is identical to the diode-connected input transistor ofthe current mirror in series with the decoding line, thus the voltagedrops are the same.

The current mirrors ensure that the current flowing through the dummyline is equal to the current flowing in the decoding line. Moreover, thedummy line is identical to the decoding line, thus the voltage on node Ais a replica of the voltage BL_(<i>).

As shown in FIG. 3, an error amplifier (or a comparator) generates theenable/disable signal PGM<0>. The generated signal controls in acontinuous mode (or in on/off mode) the relative selection/deselectiontransistor. If the voltage BL_(<i>) decreases because the voltage dropΔV(I_(P)) increases, the voltage on the node A decreases. Theoperational amplifier will then increase the amplitude of the outputselection/deselection signal PGM<0>. The voltage applied to the seriesof decoding transistors and also to node A (drain of the cell) willincrease. This compensates the sensed decrease in voltage.

Of course, the operational amplifier may alternatively be substituted bya comparator that generates in an on/off mode the signal PGM<0>. Theactive level of the voltage PGM<0> should be such to make the voltageBL_(<i>) exceed the steady-state reference voltage VREF. In doing so, inthe bit-line conduction on-phases, during which the voltage on the celltends to exceed the reference voltage VREF, is alternate with off-phasesduring which the voltage drop on the cell tends to fall below thereference voltage VREF.

A closed loop circuit for generating a regulated signal PGM, asillustrated in FIG. 3 for example, is required for each bit-line. Forthe memory device of FIG. 1, 16 such circuits including 16 dummy linesconnected as in FIG. 3 are needed for keeping at a desired referencevoltage VREF all the bit-line voltages BL_(<i>) for the 16*N*M*L memorycells.

The total current I_(TOT/BIT) delivered by the charge pump circuit is$I_{{TOT}/{BIT}} = {{2I_{P0}} + {\frac{1}{K}I_{P0}}}$where I_(P0) is the total current delivered by the charge pump circuitfor the device of FIG. 1, and 1/K is the mirror ratio of the currentmirror in series with the decoding path in the device of FIG. 3.

To reduce the total current I_(TOT/BIT) requirement, current mirrorshaving a relatively small mirror ratio 1/K are formed. This also resultsin a savings of the occupied silicon area. For instance, by choosingK=10, the total current I_(TOT/BIT) requirement is practically twice thecurrent delivered by the charge pump circuit as in the prior artarchitecture of FIG. 1.

Thus, the invention may imply doubling the programming currentabsorption for each bit I_(P<i>), but in most cases this is toleratedeven by the same charge pump circuits being used. The increase of powerconsumption is a fair price to pay to significantly enhance theprecision with which the voltage BL_(<i>) acting on each addressed cellis determined with the circuit of the present invention.

1-6. (canceled)
 7. A bit-line selection circuit for a memory devicecomprising: a decoding line including a regulated voltage node receivinga regulated voltage and a programming voltage node providing aprogramming voltage for a cell in the memory device, said decoding linecomprising at least one input transistor connected to the regulatedvoltage node and being controlled by an enable/disable signal; a dummyline identical to said decoding line and being controlled by theenable/disable signal; an equalization circuit connected between saiddecoding and dummy lines for setting a current in said dummy line equalto a current in said decoding line; and a regulating circuit forregulating the programming voltage generated at the programming voltagenode of said decoding line by compensating for differences between theprogramming voltage and a reference voltage, said regulating circuithaving a first input for receiving the reference voltage, a second inputfor receiving a sensed voltage on the programming voltage node in saiddummy line, and an output for providing the enable/disable signal.
 8. Abit-line selection circuit according to claim 7, wherein said regulationcircuit comprises an operational amplifier having a non-inverting inputcorresponding to the first input, and an inverting input correspondingto the second input.
 9. A bit-line selection circuit according to claim8, wherein the enable/disable signal has a null value when theprogramming voltage exceeds the reference voltage, and a non-null valuewhen the reference voltage exceeds the programming voltage.
 10. Abit-line selection circuit according to claim 7, wherein saidequalization circuit comprises: a first current mirror connecting saiddecoding line to the regulated voltage node, and comprising an inputtransistor in series with said decoding line; a diode-connected loadtransistor identical with the input transistor of said first currentmirror for connecting said dummy line to the regulated voltage node; anda second current mirror connecting said dummy line to a voltagereference node, and comprising an input transistor in series with saiddummy line, said second current mirror having a mirror ratio that is areciprocal of the mirror ratio of said first current mirror.
 11. Abit-line selection circuit according to claim 10, wherein the mirrorratio of said first current mirror is less than 0.1.
 12. A memorycomprising: an array of non-volatile memory cells; and a plurality ofbit-line selection circuits connected to said array of non-volatilememory cells, each bit line selection circuit comprising a decoding lineincluding a regulated voltage node and a programming voltage nodegenerating a programming voltage for a corresponding non-volatile memorycell, said decoding line comprising at least one input transistorconnected to the regulated voltage node and being controlled by anenable/disable signal, a dummy line identical to said decoding line andbeing controlled by the enable/disable signal, an equalization circuitconnected between said decoding and dummy lines for setting a current insaid dummy line equal to a current in said decoding line, and aregulating circuit for regulating the programming voltage generated atthe programming voltage node of said decoding line by compensating fordifferences between a programming voltage and the reference voltage,said regulating circuit having a first input for receiving the referencevoltage, a second input for receiving a sensed voltage on theprogramming voltage node in said dummy line, and an output for providingthe enable/disable signal.
 13. A memory according to claim 12, whereinsaid regulation circuit comprises an operational amplifier having anon-inverting input corresponding to the first input, and an invertinginput corresponding to the second input.
 14. A memory according to claim13, wherein the enable/disable signal has a null value when theprogramming voltage exceeds the reference voltage, and a non-null valuewhen the reference voltage exceeds the programming voltage.
 15. A memoryaccording to claim 12, wherein said equalization circuit comprises: afirst current mirror connecting said decoding line to the regulatedvoltage node, and comprising an input transistor in series with saiddecoding line; a diode-connected load transistor identical with theinput transistor of said first current mirror for connecting said dummyline to the regulated voltage node; and a second current mirrorconnecting said dummy line to a voltage reference node, and comprisingan input transistor in series with said dummy line, said second currentmirror having a mirror ratio that is a reciprocal of the mirror ratio ofsaid first current mirror.
 16. A memory according to claim 15, whereinthe mirror ratio of said first current mirror is less than 0.1.
 17. Amemory comprising: a charge pump providing a regulated voltage to aregulated voltage node; an array of memory cells arranged in rows andcolumns; and a plurality of bit-line selection circuits connected to thecolumns of said array of memory cells, each bit line selection circuitcomprising a decoding line including the regulated voltage node and aprogramming voltage node and generating a programming voltage for amemory cell in a corresponding bit line, said decoding line comprisingat least one input transistor connected to the regulated voltage nodeand being controlled by an enable/disable signal, a dummy line identicalto said decoding line and being controlled by the enable/disable signal,at least one current mirror connected between said decoding and dummylines for setting a current in said dummy line equal to a current insaid decoding line, and a comparator having a first input for receivinga reference voltage, a second input for receiving a sensed voltage onthe programming voltage node in said dummy line, and an output forproviding the enable/disable signal which compensates for differencesbetween the programming voltage and the reference voltage.
 18. A memoryaccording to claim 17, wherein said comparator regulates the programmingvoltage generated at the programming voltage node in said decoding line,and has a non-inverting input corresponding to the first input and aninverting input corresponding to the second input.
 19. A memoryaccording to claim 18, wherein the enable/disable signal has a nullvalue when the programming voltage exceeds the reference voltage, and anon-null value when the reference voltage exceeds the programmingvoltage.
 20. A memory according to claim 17, wherein said at least onecurrent mirror comprises: a first current mirror connecting saiddecoding line to the regulated voltage node, and comprising an inputtransistor in series with said decoding line; and a second currentmirror connecting said dummy line to a voltage reference node, andcomprising an input transistor in series with said dummy line, saidsecond current mirror having a mirror ratio that is a reciprocal of themirror ratio of said first current mirror.
 21. A memory according toclaim 20, further comprising a diode-connected load transistor identicalwith the input transistor of said first current mirror for connectingsaid dummy line to the regulated voltage node.
 22. A memory according toclaim 20, wherein the mirror ratio of said first current mirror is lessthan 0.1.
 23. A method for selecting a memory cell within an array ofmemory cells using at least one bit-line selection circuit comprising adecoding line including a regulated voltage node and a programmingvoltage node, the decoding line comprising at least one input transistorconnected to the regulated voltage node and being controlled by anenable/disable signal, and a dummy line identical to the decoding lineand being controlled by the enable/disable signal, the methodcomprising: setting a current in the dummy line equal to a current inthe decoding line; and regulating a programming voltage generated at theprogramming voltage node of the decoding line using a regulating circuitto compensate for differences between the programming voltage and thereference voltage.
 24. A method according to claim 23, wherein theregulating circuit comprises an operational amplifier having anon-inverting input corresponding to the first input, and an invertinginput corresponding to the second input.
 25. A method according to claim24, wherein the enable/disable signal has a null value when theprogramming voltage exceeds the reference voltage, and a non-null valuewhen the reference voltage exceeds the programming voltage.
 26. A methodaccording to claim 23, wherein setting the current is based upon: afirst current mirror connecting the decoding line to the regulatedvoltage node, and comprising an input transistor in series with thedecoding line; a diode-connected load transistor identical with theinput transistor of the first current mirror for connecting the dummyline to the regulated voltage node; and a second current mirrorconnecting the dummy line to a voltage reference node, and comprising aninput transistor in series with the dummy line, the second currentmirror having a mirror ratio that is a reciprocal of the mirror ratio ofthe first current mirror.
 27. A method according to claim 26, whereinthe mirror ratio of the first current mirror is less than 0.1.